mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	Skip $inout transformation if not a PI
This commit is contained in:
		
							parent
							
								
									78c0246d4a
								
							
						
					
					
						commit
						b19fc8839b
					
				
					 1 changed files with 5 additions and 3 deletions
				
			
		|  | @ -542,10 +542,12 @@ struct XAigerWriter | ||||||
| 				undriven_bits.erase(bit); | 				undriven_bits.erase(bit); | ||||||
| 			} | 			} | ||||||
| 
 | 
 | ||||||
| 		// For inout ports, or keep-ed wires, then create a new wire with an
 | 		// For inout ports, or keep-ed wires, that end up as both a PI and a
 | ||||||
| 		// $inout.out suffix, make it a PO driven by the existing inout, and
 | 		// PO, then create a new PO with an $inout.out suffix that is driven
 | ||||||
| 		// inherit existing inout's drivers
 | 		// by the existing inout, and inherit its drivers
 | ||||||
| 		for (auto bit : inout_bits) { | 		for (auto bit : inout_bits) { | ||||||
|  | 			if (!input_bits.count(bit)) | ||||||
|  | 				continue; | ||||||
| 			RTLIL::Wire *wire = bit.wire; | 			RTLIL::Wire *wire = bit.wire; | ||||||
| 			RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); | 			RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); | ||||||
| 			RTLIL::Wire *new_wire = module->wire(wire_name); | 			RTLIL::Wire *new_wire = module->wire(wire_name); | ||||||
|  |  | ||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue