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Progress in presentation

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This commit is contained in:
Clifford Wolf 2014-06-21 16:33:33 +02:00
parent 1c85584fe5
commit b18fa95d2f
9 changed files with 188 additions and 23 deletions
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17
manual/PRESENTATION_ExOth/equiv.ys Normal file
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# read test design
read_verilog ../PRESENTATION_ExSyn/techmap_01.v
hierarchy -top test
# create two version of the design: test_orig and test_mapped
copy test test_orig
rename test test_mapped
# apply the techmap only to test_mapped
techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
# create a miter circuit to test equivialence
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
flatten miter
# run equivialence check
sat -verify -prove-asserts -show-inputs -show-outputs miter