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Progress in presentation

This commit is contained in:
Clifford Wolf 2014-06-21 16:33:33 +02:00
parent 1c85584fe5
commit b18fa95d2f
9 changed files with 188 additions and 23 deletions

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module axis_master(aclk, aresetn, tvalid, tready, tdata);
input aclk, aresetn, tready;
output reg tvalid;
output reg [7:0] tdata;
reg [31:0] state;
always @(posedge aclk) begin
if (!aresetn) begin
state <= 314159265;
tvalid <= 0;
tdata <= 'bx;
end else begin
if (tvalid && tready)
tvalid <= 0;
if (!tvalid || !tready) begin
// ^- should be not inverted!
state = state ^ state << 13;
state = state ^ state >> 7;
state = state ^ state << 17;
if (state[9:8] == 0) begin
tvalid <= 1;
tdata <= state;
end
end
end
end
endmodule