Arith tree - parallel prefix.

2026-05-29 13:26:31 +00:00 · 2026-05-20 14:10:08 +02:00 · 2026-05-20 14:10:08 +02:00 · b17792c451
commit b17792c451
parent 536a117ede
8 changed files with 150 additions and 89 deletions
--- a/tests/arith_tree/arith_tree_add_chains.ys
+++ b/tests/arith_tree/arith_tree_add_chains.ys
@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -23,7 +23,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -38,7 +38,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -55,7 +55,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 14 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -76,7 +76,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 2 t:$alu
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@ -102,7 +102,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 3 t:$alu
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@ -131,7 +131,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 4 t:$alu
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@ -151,7 +151,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@ -170,7 +170,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@ -189,7 +189,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
--- a/tests/arith_tree/arith_tree_defaults.ys
+++ b/tests/arith_tree/arith_tree_defaults.ys
@ -31,14 +31,11 @@ proc
 alumacc
 opt
 arith_tree
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 0 t:$macc t:$macc_v2 %u
-select -assert-count 0 t:$mul
+stat
 arith_tree
-select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
-select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$macc
+select -assert-count 0 t:$macc_v2
 select -assert-count 0 t:$mul
 design -reset

@ -55,8 +52,9 @@ proc
 equiv_opt arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
-select -assert-count 2 t:$fa c:*emit_compressor_42* %i
-select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+select -assert-none t:$add
+select -assert-min 1 t:$_AND_
+select -assert-min 1 t:$_XOR_
 design -reset

 read_verilog <<EOT
@ -72,7 +70,7 @@ proc
 equiv_opt arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
-select -assert-count 2 t:$fa c:*emit_compressor_42* %i
 select -assert-count 1 t:$add
 select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
 design -reset
--- a/tests/arith_tree/arith_tree_edge_cases.ys
+++ b/tests/arith_tree/arith_tree_edge_cases.ys
@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -23,7 +23,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -38,7 +38,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -56,7 +56,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -71,7 +71,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -86,7 +86,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -101,7 +101,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -117,7 +117,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 4 t:$fa
 select -assert-count 2 t:$add
 design -reset
@ -141,7 +141,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@ -158,7 +158,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@ -177,7 +177,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@ -196,7 +196,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@ -215,12 +215,11 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-none t:$mul
-select -assert-count 7 t:$fa
-select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+select -assert-min 1 t:$fa
 design -reset

 read_verilog <<EOT
@ -255,7 +254,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$fa
 select -assert-count 2 t:$alu
@ -273,7 +272,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$fa
 design -reset
@ -293,7 +292,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@ -313,7 +312,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@ -342,7 +341,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-min 1 t:$dff
 design -reset
@ -361,7 +360,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@ -381,7 +380,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@ -401,7 +400,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@ -420,12 +419,11 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-none t:$mul
-select -assert-count 8 t:$fa
-select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+select -assert-min 1 t:$fa
 design -reset

 read_verilog <<EOT
--- a/tests/arith_tree/arith_tree_final_adder.ys
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@ -10,9 +10,10 @@ hierarchy -auto-top
 proc
 equiv_opt arith_tree -final auto
 design -load postopt
-select -assert-count 1 t:$add
+select -assert-none t:$add
 select -assert-count 2 t:$fa
-select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+select -assert-min 1 t:$_AND_
+select -assert-min 1 t:$_XOR_
 design -reset

 read_verilog <<EOT
@ -30,6 +31,7 @@ design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 2 t:$fa
 select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
 design -reset

 read_verilog <<EOT
@ -46,6 +48,7 @@ equiv_opt arith_tree -final ripple
 design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
 design -reset

 read_verilog <<EOT
@ -60,24 +63,9 @@ hierarchy -auto-top
 proc
 equiv_opt arith_tree -final prefix
 design -load postopt
-select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
-design -reset
-
-read_verilog <<EOT
-module final_elarith(
-	input [15:0] a, b, c, d,
-	output [15:0] y
-);
-	assign y = a + b + c + d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-arith_tree -final elarith
-select -assert-count 0 t:$add
-select -assert-count 1 t:\AddCfast
-select -assert-count 2 t:$fa
-select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-none t:$add
+select -assert-min 1 t:$_AND_
+select -assert-min 1 t:$_XOR_
 design -reset

 read_verilog <<EOT
--- a/tests/arith_tree/arith_tree_idempotent.ys
+++ b/tests/arith_tree/arith_tree_idempotent.ys
@ -9,11 +9,11 @@ EOT
 hierarchy -auto-top
 proc

-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add

-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
@ -32,13 +32,13 @@ proc
 alumacc
 opt_clean

-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
 select -assert-none t:$alu

-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
--- a/tests/arith_tree/arith_tree_sub_chains.ys
+++ b/tests/arith_tree/arith_tree_sub_chains.ys
@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@ -25,7 +25,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@ -42,7 +42,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 3 t:$not
@ -59,7 +59,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 4 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 2 t:$not
@ -76,7 +76,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 2 t:$not
@ -94,7 +94,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@ -113,7 +113,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@ -133,7 +133,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@ -153,7 +153,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@ -173,7 +173,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@ -193,7 +193,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-min 1 t:$fa
@ -212,7 +212,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-min 1 t:$fa
@ -232,7 +232,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-count 4 t:$fa