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	cellmatch: Rename the special design to $cellmatch
				
					
				
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					 2 changed files with 3 additions and 3 deletions
				
			
		|  | @ -136,7 +136,7 @@ struct CellmatchPass : Pass { | ||||||
| 		log("selected modules and a module from the secondary design <design>. For every such\n"); | 		log("selected modules and a module from the secondary design <design>. For every such\n"); | ||||||
| 		log("correspondence found, a techmap rule is generated for mapping instances of the\n"); | 		log("correspondence found, a techmap rule is generated for mapping instances of the\n"); | ||||||
| 		log("former to instances of the latter. This techmap rule is saved in yet another\n"); | 		log("former to instances of the latter. This techmap rule is saved in yet another\n"); | ||||||
| 		log("design called '$cellmatch_map', which is created if non-existent.\n"); | 		log("design called '$cellmatch', which is created if non-existent.\n"); | ||||||
| 		log("\n"); | 		log("\n"); | ||||||
| 		log("This pass restricts itself to combinational modules. Modules are functionally\n"); | 		log("This pass restricts itself to combinational modules. Modules are functionally\n"); | ||||||
| 		log("equivalent as long as their truth tables are identical upto a permutation of\n"); | 		log("equivalent as long as their truth tables are identical upto a permutation of\n"); | ||||||
|  | @ -192,7 +192,7 @@ struct CellmatchPass : Pass { | ||||||
| 			targets[p_classes].push_back(Target{m, luts}); | 			targets[p_classes].push_back(Target{m, luts}); | ||||||
| 		} | 		} | ||||||
| 
 | 
 | ||||||
| 		auto r = saved_designs.emplace("$cellmatch_map", nullptr); | 		auto r = saved_designs.emplace("$cellmatch", nullptr); | ||||||
| 		if (r.second) | 		if (r.second) | ||||||
| 			r.first->second = new Design; | 			r.first->second = new Design; | ||||||
| 		Design *map_design = r.first->second; | 		Design *map_design = r.first->second; | ||||||
|  |  | ||||||
|  | @ -61,7 +61,7 @@ prep | ||||||
| cellmatch -lib gatelib FA A:gate | cellmatch -lib gatelib FA A:gate | ||||||
| 
 | 
 | ||||||
| design -save gold | design -save gold | ||||||
| techmap -map %$cellmatch_map | techmap -map %$cellmatch | ||||||
| design -save gate | design -save gate | ||||||
| 
 | 
 | ||||||
| select -assert-none ripple_carry/t:FA | select -assert-none ripple_carry/t:FA | ||||||
|  |  | ||||||
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