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synth_analogdevices: update timing model and tests

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Lofty 2025-11-10 13:19:12 +00:00
parent 1ceb5b2930
commit b136a3c417
27 changed files with 213 additions and 617 deletions
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22
tests/arch/analogdevices/dsp_abc9.ys
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@ -20,19 +20,19 @@ EOT
synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
opt -full -fine
select -assert-count 1 t:$mul
select -assert-count 2 t:$mul
select -assert-count 0 t:* t:$mul %D
design -reset
read_verilog -icells -formal <<EOT
module top(output [42:0] P);
\$__MUL25X18 mul (.A(42), .B(42), .Y(P));
module top(output [43:0] P);
\$__MUL22X22 mul (.A(42), .B(42), .Y(P));
assert property (P == 42*42);
endmodule
EOT
async2sync
techmap -map +/analogdevices/xc7_dsp_map.v
techmap -map +/analogdevices/dsp_map.v
verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
@ -40,17 +40,3 @@ opt -full -fine
select -assert-count 0 t:* t:$assert %d
sat -verify -prove-asserts
design -reset
read_verilog <<EOT
module top(input signed [29:0] A, input signed [17:0] B, output signed [47:0] P);
wire [47:0] casc;
DSP48E1 #(.AREG(1)) u1(.A(A), .B(B), .PCOUT(casc));
DSP48E1 #(.AREG(1)) u2(.A(A), .B(B), .PCIN(casc), .P(P));
endmodule
EOT
synth_analogdevices -run :prepare
abc9
clean
check
logger -expect-no-warnings