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coolrunner2: Add a few more primitives

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These cannot be inferred yet, but add them to cells_sim.v for now
This commit is contained in:
Robert Ou 2017-06-25 23:56:16 -07:00
parent 36b75dfcb7
commit b102c0e254
1 changed files with 110 additions and 0 deletions
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110
techlibs/coolrunner2/cells_sim.v
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@ -134,3 +134,113 @@ module LDCP_N (G, PRE, CLR, D, Q);
Q <= 1; Q <= 1;
end end
endmodule endmodule
module BUFG(I, O);
input I;
output O;
assign O = I;
endmodule
module BUFGSR(I, O);
input I;
output O;
assign O = I;
endmodule
module BUFGTS(I, O);
input I;
output O;
assign O = I;
endmodule
module FDDCP (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module FTCP (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FTCP_N (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FTDCP (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule