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tests: test cxxrtl against iverilog (and uncover bug!)

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Charlotte 2023-06-28 11:51:18 +10:00 • committed by Marcelina Kościelnicka
parent 095b093f4a
commit b0f69f2cd5
5 changed files with 276 additions and 1 deletions
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14
tests/fmt/always_full_tb.v Normal file
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module always_full_tb;
reg clk = 0;
wire fin;
always_full uut (.clk(clk), .fin(fin));
always begin
#1 clk <= ~clk;
if (fin) $finish;
end
endmodule