From b0eb50be1b9036418bb43f086225f9a72bc2c0f3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Sat, 23 May 2026 00:11:16 +0200 Subject: [PATCH] fixup! patch: working multi-cell signorm invariant --- kernel/rtlil_bufnorm.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index 55bf9cccb..93f800f4f 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -1123,7 +1123,7 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) } if (yosys_xtrace) { - log("#X# Connect %s.%s.%s = %s (%d)\n", this->module ? this->module : "PATCH", this, portname.unescape(), log_signal(signal), GetSize(signal)); + log("#X# Connect %s.%s.%s = %s (%d)\n", this->module ? this->module->name.unescape() : "PATCH", this, portname.unescape(), log_signal(signal), GetSize(signal)); log_backtrace("-X- ", yosys_xtrace-1); }