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Added lutram

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Lofty 2024-03-01 13:41:25 +01:00 • committed by Miodrag Milanovic
parent 5d898ab223
commit b0c4add642
7 changed files with 161 additions and 29 deletions
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51
techlibs/nanoxplore/cells_sim.v
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@ -9,6 +9,7 @@ assign O = I1 ? s3[1] : s3[0];
endmodule
(* abc9_box, lib_whitebox *)
module NX_DFF(input I, CK, L, R, output reg O);
parameter dff_ctxt = 1'bx;
@ -34,8 +35,58 @@ always @(posedge clock, posedge async_reset)
endmodule
(* abc9_box, lib_whitebox *)
module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
parameter add_carry = 0;
assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI;
endmodule
(* abc9_box, lib_whitebox *)
module NX_XRFB_64x18(input WCK, input [17:0] I, input [5:0] RA, WA, input WE, WEA, output [17:0] O);
parameter wck_edge = 1'b0;
parameter mem_ctxt = 1152'b0;
reg [17:0] mem [63:0];
integer i;
initial begin
for (i = 0; i < 64; i = i + 1)
mem[i] = mem_ctxt[18*i +: 18];
end
wire clock = WCK ^ wck_edge;
always @(posedge clock)
if (WE && WEA)
mem[WA] <= I;
assign O = mem[RA];
endmodule
(* abc9_box, lib_whitebox *)
module NX_XRFB_32x36(input WCK, input [35:0] I, input [4:0] RA, WA, input WE, WEA, output [35:0] O);
parameter wck_edge = 1'b0;
parameter mem_ctxt = 1152'b0;
reg [35:0] mem [31:0];
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = mem_ctxt[36*i +: 36];
end
wire clock = WCK ^ wck_edge;
always @(posedge clock)
if (WE && WEA)
mem[WA] <= I;
assign O = mem[RA];
endmodule