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Added "init" attribute support to verilog backend

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This commit is contained in:
Clifford Wolf 2015-04-04 18:06:52 +02:00
parent 0737bf5fb8
commit b0c0ede879
1 changed files with 5 additions and 0 deletions
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5
backends/verilog/verilog_backend.cc
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@ -299,6 +299,11 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
else if (!wire->port_input && !wire->port_output) else if (!wire->port_input && !wire->port_output)
f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
if (wire->attributes.count("\\init")) {
f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
dump_const(f, wire->attributes.at("\\init"));
f << stringf(";\n");
}
#endif #endif
} }