mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
Code Activity

Add new builtin FF types

Browse source 
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
This commit is contained in:
Marcelina Kościelnicka 2020-04-08 21:42:50 +02:00
parent 8c4cb1885b
commit b0bee396a8
8 changed files with 2736 additions and 70 deletions
Download patch file Download diff file Expand all files Collapse all files

153
techlibs/common/gen_fine_ffs.py
View file

@ -108,6 +108,31 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set} and {E:negative|positive}
//- polarity clock enable.
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - - {R:0|1} - | {V:0|1}
//- d {C:\\|/} - {E:0|1} | d
//- - - - - | q
//-
module \$_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
if (R == {R:0|1})
Q <= {V:0|1};
else if (E == {E:0|1})
Q <= D;
end
endmodule
""",
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive}
@ -136,6 +161,110 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set, {R:negative|positive}
//- polarity reset and {E:negative|positive} polarity clock enable.
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - - {R:0|1} - - | 0
//- - {S:0|1} - - - | 1
//- {C:\\|/} - - {E:0|1} d | d
//- - - - - - | q
//-
module \$_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q);
input C, S, R, E, D;
output reg Q;
always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
if (R == {R:0|1})
Q <= 0;
else if (S == {S:0|1})
Q <= 1;
else if (E == {E:0|1})
Q <= D;
end
endmodule
""",
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set}.
//-
//- Truth table: D C R | Q
//- -------+---
//- - {C:\\|/} {R:0|1} | {V:0|1}
//- d {C:\\|/} - | d
//- - - - | q
//-
module \$_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
input D, C, R;
output reg Q;
always @({C:neg|pos}edge C) begin
if (R == {R:0|1})
Q <= {V:0|1};
else
Q <= D;
end
endmodule
""",
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
//- polarity clock enable (with {V:reset|set} having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - {C:\\|/} {R:0|1} - | {V:0|1}
//- d {C:\\|/} - {E:0|1} | d
//- - - - - | q
//-
module \$_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @({C:neg|pos}edge C) begin
if (R == {R:0|1})
Q <= {V:0|1};
else if (E == {E:0|1})
Q <= D;
end
endmodule
""",
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
//- polarity clock enable (with clock enable having priority).
//-
//- Truth table: D C R E | Q
//- ---------+---
//- - {C:\\|/} {R:0|1} {E:0|1} | {V:0|1}
//- d {C:\\|/} - {E:0|1} | d
//- - - - - | q
//-
module \$_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
input D, C, R, E;
output reg Q;
always @({C:neg|pos}edge C) begin
if (E == {E:0|1}) begin
if (R == {R:0|1})
Q <= {V:0|1};
else
Q <= D;
end
end
endmodule
""",
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_{E:N|P}_ (E, D, Q)
//-
//- A {E:negative|positive} enable D-type latch.
@ -157,6 +286,30 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q)
//-
//- A {E:negative|positive} enable D-type latch with {R:negative|positive} polarity {V:reset|set}.
//-
//- Truth table: E R D | Q
//- -------+---
//- - {R:0|1} - | {V:0|1}
//- {E:0|1} - d | d
//- - - - | q
//-
module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
input E, R, D;
output reg Q;
always @* begin
if (R == {E:0|1})
Q <= {V:0|1};
else if (E == {E:0|1})
Q <= D;
end
endmodule
""",
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q)
//-
//- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive}