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Add new builtin FF types
The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
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8 changed files with 2736 additions and 70 deletions
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@ -108,6 +108,31 @@ endmodule
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set} and {E:negative|positive}
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//- polarity clock enable.
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//-
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//- Truth table: D C R E | Q
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//- ---------+---
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//- - - {R:0|1} - | {V:0|1}
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//- d {C:\\|/} - {E:0|1} | d
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//- - - - - | q
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//-
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module \$_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
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input D, C, R, E;
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output reg Q;
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always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive}
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@ -136,6 +161,110 @@ endmodule
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set, {R:negative|positive}
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//- polarity reset and {E:negative|positive} polarity clock enable.
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//-
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//- Truth table: C S R E D | Q
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//- -----------+---
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//- - - {R:0|1} - - | 0
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//- - {S:0|1} - - - | 1
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//- {C:\\|/} - - {E:0|1} d | d
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//- - - - - - | q
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//-
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module \$_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q);
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input C, S, R, E, D;
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output reg Q;
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always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
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if (R == {R:0|1})
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Q <= 0;
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else if (S == {S:0|1})
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Q <= 1;
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set}.
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//-
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//- Truth table: D C R | Q
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//- -------+---
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//- - {C:\\|/} {R:0|1} | {V:0|1}
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//- d {C:\\|/} - | d
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//- - - - | q
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//-
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module \$_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
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input D, C, R;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
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//- polarity clock enable (with {V:reset|set} having priority).
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//-
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//- Truth table: D C R E | Q
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//- ---------+---
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//- - {C:\\|/} {R:0|1} - | {V:0|1}
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//- d {C:\\|/} - {E:0|1} | d
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//- - - - - | q
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//-
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module \$_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
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input D, C, R, E;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
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//-
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//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
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//- polarity clock enable (with clock enable having priority).
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//-
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//- Truth table: D C R E | Q
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//- ---------+---
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//- - {C:\\|/} {R:0|1} {E:0|1} | {V:0|1}
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//- d {C:\\|/} - {E:0|1} | d
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//- - - - - | q
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//-
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module \$_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
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input D, C, R, E;
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output reg Q;
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always @({C:neg|pos}edge C) begin
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if (E == {E:0|1}) begin
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if (R == {R:0|1})
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Q <= {V:0|1};
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else
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Q <= D;
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end
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCH_{E:N|P}_ (E, D, Q)
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//-
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//- A {E:negative|positive} enable D-type latch.
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@ -157,6 +286,30 @@ endmodule
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q)
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//-
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//- A {E:negative|positive} enable D-type latch with {R:negative|positive} polarity {V:reset|set}.
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//-
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//- Truth table: E R D | Q
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//- -------+---
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//- - {R:0|1} - | {V:0|1}
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//- {E:0|1} - d | d
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//- - - - | q
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//-
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module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
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input E, R, D;
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output reg Q;
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always @* begin
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if (R == {E:0|1})
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Q <= {V:0|1};
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else if (E == {E:0|1})
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Q <= D;
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end
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endmodule
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""",
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"""
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q)
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//-
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//- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive}
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