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Support importing verilog configurations using Verific

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This commit is contained in:
Miodrag Milanovic 2022-11-25 13:02:11 +01:00
parent fc2f622a27
commit b0be19c126
3 changed files with 40 additions and 5 deletions
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2
passes/hierarchy/hierarchy.cc
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@ -960,7 +960,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr && !load_top_mod.empty()) {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) {
verific_import(design, parameters, load_top_mod);
load_top_mod = verific_import(design, parameters, load_top_mod);
top_mod = design->module(RTLIL::escape_id(load_top_mod));
}
#endif