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Merge branch 'master' of github.com:cliffordwolf/yosys

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This commit is contained in:
Clifford Wolf 2017-01-26 08:59:26 +01:00
parent fea528280b b54972c112
commit b0a430f601
2 changed files with 1 additions and 4 deletions
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1
kernel/rtlil.cc
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@ -2050,6 +2050,7 @@ RTLIL::Memory::Memory()
hashidx_ = hashidx_count; hashidx_ = hashidx_count;
width = 1; width = 1;
start_offset = 0;
size = 0; size = 0;
} }

4
passes/hierarchy/hierarchy.cc
View file

@ -175,16 +175,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
{ {
filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v"; filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
if (check_file_exists(filename)) { if (check_file_exists(filename)) {
std::vector<std::string> args;
args.push_back(filename);
Frontend::frontend_call(design, NULL, filename, "verilog"); Frontend::frontend_call(design, NULL, filename, "verilog");
goto loaded_module; goto loaded_module;
} }
filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
if (check_file_exists(filename)) { if (check_file_exists(filename)) {
std::vector<std::string> args;
args.push_back(filename);
Frontend::frontend_call(design, NULL, filename, "ilang"); Frontend::frontend_call(design, NULL, filename, "ilang");
goto loaded_module; goto loaded_module;
} }