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Only pack out registers if \init is zero or x; then remove \init from PREG

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This commit is contained in:
Eddie Hung 2019-09-10 21:33:14 -07:00
parent 37a34eeb04
commit b08797da6b
2 changed files with 18 additions and 4 deletions
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10
passes/pmgen/xilinx_dsp.cc
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@ -451,6 +451,16 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
P.replace(pm.sigmap(D), Q); P.replace(pm.sigmap(D), Q);
st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
for (auto c : Q.chunks()) {
auto it = c.wire->attributes.find("\\init");
if (it == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
}
}
cell->setParam("\\PREG", State::S1); cell->setParam("\\PREG", State::S1);
} }

12
passes/pmgen/xilinx_dsp.pmg
View file

@ -290,8 +290,8 @@ endmatch
code argQ code argQ
if (ff) { if (ff) {
for (auto b : argQ) for (auto c : argQ.chunks())
if (b.wire->get_bool_attribute(\keep)) if (c.wire->get_bool_attribute(\keep))
reject; reject;
if (clock != SigBit()) { if (clock != SigBit()) {
@ -447,9 +447,13 @@ code
if (dff) { if (dff) {
dffQ = port(dff, \Q); dffQ = port(dff, \Q);
for (auto b : dffQ) for (auto c : dffQ.chunks()) {
if (b.wire->get_bool_attribute(\keep)) if (c.wire->get_bool_attribute(\keep))
reject; reject;
Const init = c.wire->attributes.at(\init, State::Sx);
if (!init.is_fully_undef() && !init.is_fully_zero())
reject;
}
if (clock != SigBit()) { if (clock != SigBit()) {
if (port(dff, \CLK) != clock) if (port(dff, \CLK) != clock)