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Only pack out registers if \init is zero or x; then remove \init from PREG

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This commit is contained in:
Eddie Hung 2019-09-10 21:33:14 -07:00
parent 37a34eeb04
commit b08797da6b
2 changed files with 18 additions and 4 deletions
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12
passes/pmgen/xilinx_dsp.pmg
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@ -290,8 +290,8 @@ endmatch
code argQ
if (ff) {
for (auto b : argQ)
if (b.wire->get_bool_attribute(\keep))
for (auto c : argQ.chunks())
if (c.wire->get_bool_attribute(\keep))
reject;
if (clock != SigBit()) {
@ -447,9 +447,13 @@ code
if (dff) {
dffQ = port(dff, \Q);
for (auto b : dffQ)
if (b.wire->get_bool_attribute(\keep))
for (auto c : dffQ.chunks()) {
if (c.wire->get_bool_attribute(\keep))
reject;
Const init = c.wire->attributes.at(\init, State::Sx);
if (!init.is_fully_undef() && !init.is_fully_zero())
reject;
}
if (clock != SigBit()) {
if (port(dff, \CLK) != clock)