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Anhijkt 2025-11-14 13:34:58 +02:00
parent a75b999f13
commit b08195a9cf
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tests/various/fsm-arst.ys
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@ -81,7 +81,7 @@ module self_rs_fsm (
localparam [7:0] S2 = 8'b11000111;
reg [7:0] next_state;
wire reset = (reset_reg || next_state == S1);
wire reset = next_state == S1;
always @(posedge clk or posedge reset) begin
if (reset) begin