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Add tests for some common techmap files.

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Marcelina Kościelnicka 2021-02-23 21:23:26 +01:00
parent cde73428b0
commit b05b98521c
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tests/techmap/dff2ff.ys Normal file
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read_verilog -icells << EOT
module top(...);
input [1:0] D;
input C;
output [1:0] Q;
always @(posedge C)
Q <= D;
endmodule
EOT
proc
equiv_opt techmap -map +/dff2ff.v