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Add tests for some common techmap files.

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Marcelina Kościelnicka 2021-02-23 21:23:26 +01:00
parent cde73428b0
commit b05b98521c
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tests/techmap/adff2dff.ys Normal file
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read_verilog -icells << EOT
module top(...);
input [1:0] D;
input C, R;
output [1:0] Q;
always @(posedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
endmodule
EOT
proc
equiv_opt -async2sync techmap -map +/adff2dff.v