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	Fixed keep attribute on wires in opt_clean
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		|  | @ -54,7 +54,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) | ||||||
| 
 | 
 | ||||||
| 	for (auto &it : module->wires) { | 	for (auto &it : module->wires) { | ||||||
| 		RTLIL::Wire *wire = it.second; | 		RTLIL::Wire *wire = it.second; | ||||||
| 		if (wire->port_output) { | 		if (wire->port_output || wire->get_bool_attribute("\\keep")) { | ||||||
| 			std::set<RTLIL::Cell*> cell_list; | 			std::set<RTLIL::Cell*> cell_list; | ||||||
| 			RTLIL::SigSpec sig = RTLIL::SigSpec(wire); | 			RTLIL::SigSpec sig = RTLIL::SigSpec(wire); | ||||||
| 			assign_map.apply(sig); | 			assign_map.apply(sig); | ||||||
|  |  | ||||||
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