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Towards DRAM support in Xilinx flow

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This commit is contained in:
Clifford Wolf 2015-04-09 08:17:14 +02:00
parent 21a1cc1b60
commit b00cad81d7
5 changed files with 78 additions and 0 deletions
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17
techlibs/xilinx/drams.txt Normal file
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bram $__XILINX_RAM32X1D
init 1
abits 5
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__XILINX_RAM32X1D
endmatch