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intel_alm: DSP inference
This commit is contained in:
Dan Ravensloft
Marcelina Kościelnicka
parent
01772dec8c
commit
b004f09018
7 changed files with 209 additions and 9 deletions
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@ -10,6 +10,8 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/al
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_sim.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
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$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
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# RAM
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49
techlibs/intel_alm/common/dsp_map.v
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49
techlibs/intel_alm/common/dsp_map.v
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@ -0,0 +1,49 @@
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module __MUL27X27(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 27;
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parameter B_WIDTH = 27;
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parameter Y_WIDTH = 54;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL27X27 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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module __MUL18X18(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL18X18 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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module __MUL9X9(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL9X9 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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35
techlibs/intel_alm/common/dsp_sim.v
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35
techlibs/intel_alm/common/dsp_sim.v
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@ -0,0 +1,35 @@
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(* abc9_box *)
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module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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endspecify
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assign Y = $signed(A) * $signed(B);
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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endspecify
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assign Y = $signed(A) * $signed(B);
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endmodule
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(* abc9_box *)
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module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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endspecify
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assign Y = $signed(A) * $signed(B);
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endmodule
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@ -129,3 +129,31 @@ output [data_width-1:0] portbdataout;
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input ena0, clk0, clk1;
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endmodule
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(* blackbox *)
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module cyclonev_mac(ax, ay, resulta);
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parameter ax_width = 9;
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parameter ay_scan_in_width = 9;
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parameter result_a_width = 18;
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parameter operation_mode = "M9x9";
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input [ax_width-1:0] ax;
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input [ay_scan_in_width-1:0] ay;
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output [result_a_width-1:0] resulta;
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endmodule
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(* blackbox *)
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module cyclone10gx_mac(ax, ay, resulta);
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parameter ax_width = 18;
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parameter ay_scan_in_width = 18;
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parameter result_a_width = 36;
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parameter operation_mode = "M18X18_FULL";
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input [ax_width-1:0] ax;
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input [ay_scan_in_width-1:0] ay;
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output [result_a_width-1:0] resulta;
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endmodule
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@ -1,9 +1,11 @@
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`ifdef cyclonev
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`define LCELL cyclonev_lcell_comb
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`define MAC cyclonev_mac
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`define MLAB cyclonev_mlab_cell
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`endif
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`ifdef cyclone10gx
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`define LCELL cyclone10gx_lcell_comb
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`define MAC cyclone10gx_mac
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`define MLAB cyclone10gx_mlab_cell
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`endif
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@ -119,3 +121,24 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
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);
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endmodule
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module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
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`MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y));
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endmodule
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module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
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`MAC #(.ax_width(18), .ay_scan_in_width(18), .result_a_width(36), .operation_mode("M18x18_FULL")) _TECHMAP_REPLACE_ (.ax(B), .ay(A), .resulta(Y));
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endmodule
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module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
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`MAC #(.ax_width(9), .ay_scan_in_width(9), .result_a_width(18), .operation_mode("M9x9")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y));
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endmodule
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@ -69,13 +69,16 @@ struct SynthIntelALMPass : public ScriptPass {
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not map multipliers to MISTRAL_MUL cells\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, family_opt, bram_type, vout_file;
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bool flatten, quartus, nolutram, nobram, dff;
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bool flatten, quartus, nolutram, nobram, dff, nodsp;
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void clear_flags() override
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{
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@ -88,6 +91,7 @@ struct SynthIntelALMPass : public ScriptPass {
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nolutram = false;
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nobram = false;
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dff = false;
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nodsp = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -130,6 +134,10 @@ struct SynthIntelALMPass : public ScriptPass {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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@ -169,9 +177,11 @@ struct SynthIntelALMPass : public ScriptPass {
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}
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if (check_label("begin")) {
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if (family_opt == "cyclonev")
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run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str()));
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@ -181,16 +191,46 @@ struct SynthIntelALMPass : public ScriptPass {
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (flatten && check_label("flatten", "(unless -noflatten)")) {
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if (check_label("coarse")) {
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run("proc");
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run("flatten");
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if (flatten || help_mode)
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run("flatten", "(skip if -noflatten)");
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run("tribuf -logic");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
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run("opt_expr");
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run("opt_clean");
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if (help_mode) {
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run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
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} else if (!nodsp) {
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// Cyclone V supports 9x9 multiplication, Cyclone 10 GX does not.
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=19 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL27X27");
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run("chtype -set $mul t:$__soft_mul");
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if (family_opt == "cyclonev") {
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18");
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run("chtype -set $mul t:$__soft_mul");
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL9X9");
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run("chtype -set $mul t:$__soft_mul");
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} else if (family_opt == "cyclone10gx") {
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18");
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run("chtype -set $mul t:$__soft_mul");
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}
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if (check_label("coarse")) {
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run("synth -run coarse -lut 6");
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run("techmap -map +/intel_alm/common/arith_alm_map.v");
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}
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run("alumacc");
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run("techmap -map +/intel_alm/common/arith_alm_map.v -map +/intel_alm/common/dsp_map.v");
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run("opt");
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run("fsm");
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run("opt -fast");
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run("memory -nomap");
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run("opt_clean");
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}
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if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
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23
tests/arch/intel_alm/mul.ys
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23
tests/arch/intel_alm/mul.ys
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@ -0,0 +1,23 @@
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read_verilog ../common/mul.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:MISTRAL_MUL9X9
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select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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# Cyclone 10 GX does not have 9x9 multipliers, so we use 18x18.
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select -assert-count 1 t:MISTRAL_MUL18X18
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select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
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