mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-31 23:34:57 +00:00
intel_alm: DSP inference
This commit is contained in:
parent
01772dec8c
commit
b004f09018
7 changed files with 209 additions and 9 deletions
|
@ -129,3 +129,31 @@ output [data_width-1:0] portbdataout;
|
|||
input ena0, clk0, clk1;
|
||||
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module cyclonev_mac(ax, ay, resulta);
|
||||
|
||||
parameter ax_width = 9;
|
||||
parameter ay_scan_in_width = 9;
|
||||
parameter result_a_width = 18;
|
||||
parameter operation_mode = "M9x9";
|
||||
|
||||
input [ax_width-1:0] ax;
|
||||
input [ay_scan_in_width-1:0] ay;
|
||||
output [result_a_width-1:0] resulta;
|
||||
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module cyclone10gx_mac(ax, ay, resulta);
|
||||
|
||||
parameter ax_width = 18;
|
||||
parameter ay_scan_in_width = 18;
|
||||
parameter result_a_width = 36;
|
||||
parameter operation_mode = "M18X18_FULL";
|
||||
|
||||
input [ax_width-1:0] ax;
|
||||
input [ay_scan_in_width-1:0] ay;
|
||||
output [result_a_width-1:0] resulta;
|
||||
|
||||
endmodule
|
Loading…
Add table
Add a link
Reference in a new issue