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xilinx: Improve flip-flop handling.

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This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
This commit is contained in:
Marcin Kościelnicki 2019-11-21 06:30:06 +01:00 • committed by Marcin Kościelnicki
parent 22dd9f107c
commit aff6ad1ce0
8 changed files with 264 additions and 71 deletions
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9
tests/arch/xilinx/adffs.ys
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@ -32,10 +32,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivale
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:LUT2
select -assert-count 1 t:FDSE
select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
select -assert-none t:BUFG t:FDSE %% t:* %D
design -load read
@ -46,6 +45,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE_1
select -assert-count 1 t:LUT2
select -assert-count 1 t:INV
select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D