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xilinx: Improve flip-flop handling.
This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
This commit is contained in:
Marcin Kościelnicki
Marcin Kościelnicki
parent
22dd9f107c
commit
aff6ad1ce0
8 changed files with 264 additions and 71 deletions
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@ -37,6 +37,8 @@
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`ifndef _NO_FFS
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// No reset.
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module \$_DFF_N_ (input D, C, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
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@ -48,6 +50,8 @@ module \$_DFF_P_ (input D, C, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// No reset, enable.
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module \$_DFFE_NP_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
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@ -59,48 +63,104 @@ module \$_DFFE_PP_ (input D, C, E, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFF_NN0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Async reset.
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module \$_DFF_NP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFF_PP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFF_NP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Async reset, enable.
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module \$__DFFE_NP0 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFE_PP0 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFE_NP1 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFE_PP1 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Sync reset.
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module \$__DFFS_NP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFS_PP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFS_NP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFS_PP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Sync reset, enable.
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module \$__DFFSE_NP0 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFSE_PP0 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFSE_NP1 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$__DFFSE_PP1 (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Latches (no reset).
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module \$_DLATCH_N_ (input E, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
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@ -112,5 +172,7 @@ module \$_DLATCH_P_ (input E, D, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Latches with reset (TODO).
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`endif
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