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Use defaultvalue for init values of input ports

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This commit is contained in:
Miodrag Milanovic 2023-06-21 13:21:34 +02:00
parent 941fa70ce1
commit aff0065646
1 changed files with 4 additions and 1 deletions
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5
frontends/verific/verific.cc
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@ -2005,7 +2005,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
initval[i] = State::Sx; initval[i] = State::Sx;
} }
if (initval.is_fully_undef()) if (wire->port_input) {
wire->attributes[ID::defaultvalue] = Const(initval);
wire->attributes.erase(ID::init);
} else if (initval.is_fully_undef())
wire->attributes.erase(ID::init); wire->attributes.erase(ID::init);
} }
} }