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Use defaultvalue for init values of input ports
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@ -2005,7 +2005,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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initval[i] = State::Sx;
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}
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if (initval.is_fully_undef())
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if (wire->port_input) {
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wire->attributes[ID::defaultvalue] = Const(initval);
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wire->attributes.erase(ID::init);
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} else if (initval.is_fully_undef())
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wire->attributes.erase(ID::init);
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}
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}
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