mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-24 16:12:33 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-11 20:02:02 +02:00
parent 8e522b08c0
commit afdae7b87e
49 changed files with 1258 additions and 891 deletions
Download patch file Download diff file Expand all files Collapse all files

10
passes/techmap/abc9_ops.cc
View file

@ -194,7 +194,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
// If derived_type is present in unmap_design, it means that it was processed previously, but found to be incompatible -- e.g. if
// it contained a non-zero initial state. In this case, continue to replace the cell type/parameters so that it has the same properties
// as a compatible type, yet will be safely unmapped later
cell->type = derived_type;
cell->type_impl = cell->module->design->twines.add(Twine{derived_type.str()});
cell->parameters.clear();
unused_derived.erase(derived_type);
}
@ -254,7 +254,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
}
cell->type = derived_type;
cell->type_impl = cell->module->design->twines.add(Twine{derived_type.str()});
cell->parameters.clear();
unused_derived.erase(derived_type);
}
@ -320,7 +320,7 @@ void prep_bypass(RTLIL::Design *design)
// Copy inst_module into map_design, with the same interface
// and duplicate $abc9$* wires for its output ports
auto map_module = map_design->addModule(cell->type);
auto map_module = map_design->addModule(cell->type.ref());
for (auto port_name : inst_module->ports) {
auto w = map_module->addWire(port_name, inst_module->wire(port_name));
if (w->port_output)
@ -459,7 +459,7 @@ void prep_dff(RTLIL::Design *design)
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
if (modules_sel.selected_whole_module(cell->type))
if (modules_sel.selected_whole_module(cell->type.ref()))
continue;
auto inst_module = design->module(cell->type);
if (!inst_module)
@ -1402,7 +1402,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::Module* box_module = design->module(existing_cell->type);
log_assert(existing_cell->parameters.empty());
log_assert(mapped_cell->type == stringf("$__boxid%d", box_module->attributes.at(ID::abc9_box_id).as_int()));
mapped_cell->type = existing_cell->type;
mapped_cell->type_impl = existing_cell->type_impl;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = existing_cell->parameters;

2
passes/techmap/extract_counter.cc
View file

@ -628,7 +628,7 @@ void counter_worker(
cell->unsetParam(ID::Y_WIDTH);
//Change the cell type
cell->type = ID($__COUNT_);
cell->type_impl = TW::$__COUNT_;
//Hook up resets
if(extract.has_reset)

2
passes/techmap/lut2bmux.cc
View file

@ -44,7 +44,7 @@ struct Lut2BmuxPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) {
if (cell->type == ID($lut)) {
cell->type = ID($bmux);
cell->type_impl = TW::$bmux;
cell->setPort(TW::S, cell->getPort(TW::A));
cell->setPort(TW::A, cell->getParam(ID::LUT));
cell->unsetParam(ID::LUT);

2
passes/techmap/shregmap.cc
View file

@ -332,7 +332,7 @@ struct ShregmapWorker
if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol);
}
first_cell->type = shreg_cell_type_str;
first_cell->type_impl = first_cell->module->design->twines.add(Twine{shreg_cell_type_str});
first_cell->setPort(q_port, last_cell->getPort(q_port));
first_cell->setParam(ID::DEPTH, depth);

4
passes/techmap/techmap.cc
View file

@ -562,7 +562,7 @@ struct TechmapWorker
}
}
cell->type = extmapper_module->name;
cell->type_impl = extmapper_module->meta_->name;
cell->parameters.clear();
if (!extern_mode || in_recursion) {
@ -933,7 +933,7 @@ struct TechmapWorker
}
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix, module, cell, m_name);
cell->type = m_name;
cell->type_impl = cell->module->design->twines.add(Twine{m_name.str()});
cell->parameters.clear();
}
else

4
passes/techmap/tribuf.cc
View file

@ -86,7 +86,7 @@ struct TribufWorker {
cell->setPort(en_port, cell->getPort(TW::S));
cell->unsetPort(TW::B);
cell->unsetPort(TW::S);
cell->type = tri_type;
cell->type_impl = cell->module->design->twines.add(Twine{tri_type.str()});
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;
@ -96,7 +96,7 @@ struct TribufWorker {
cell->setPort(en_port, module->Not(NEW_TWINE, cell->getPort(TW::S)));
cell->unsetPort(TW::B);
cell->unsetPort(TW::S);
cell->type = tri_type;
cell->type_impl = cell->module->design->twines.add(Twine{tri_type.str()});
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;