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Fix tabulation

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This commit is contained in:
Eddie Hung 2019-02-08 13:17:02 -08:00
parent aa66d8f12f
commit afc3c4b613
1 changed files with 28 additions and 28 deletions
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8
frontends/aiger/aigerparse.cc
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@ -366,10 +366,6 @@ struct AigerFrontend : public Frontend {
log("\n"); log("\n");
log(" -module_name <module_name>\n"); log(" -module_name <module_name>\n");
log(" Name of module to be created (default: <filename>)" log(" Name of module to be created (default: <filename>)"
log("\n");
log(" -clk_name <wire_name>\n");
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
log(" this name (default: clk)\n");
#ifdef _WIN32 #ifdef _WIN32
"top" // FIXME "top" // FIXME
#else #else
@ -377,6 +373,10 @@ struct AigerFrontend : public Frontend {
#endif #endif
")\n"); ")\n");
log("\n"); log("\n");
log(" -clk_name <wire_name>\n");
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
log(" this name (default: clk)\n");
log("\n");
} }
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {