mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 01:54:10 +00:00
Code Activity

Exclude primary inputs from quiv_make rewiring

Browse source 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-05-04 18:54:10 +02:00 committed by Jannis Harder
parent 381ce66f58
commit afa5e6bb53
1 changed files with 7 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
passes/equiv/equiv_make.cc
View file

@ -137,6 +137,7 @@ struct EquivMakeWorker
{ {
SigMap assign_map(equiv_mod); SigMap assign_map(equiv_mod);
SigMap rd_signal_map; SigMap rd_signal_map;
SigPool primary_inputs;
// list of cells without added $equiv cells // list of cells without added $equiv cells
auto cells_list = equiv_mod->cells().to_vector(); auto cells_list = equiv_mod->cells().to_vector();
@ -252,6 +253,9 @@ struct EquivMakeWorker
gate_wire->port_input = false; gate_wire->port_input = false;
equiv_mod->connect(gold_wire, wire); equiv_mod->connect(gold_wire, wire);
equiv_mod->connect(gate_wire, wire); equiv_mod->connect(gate_wire, wire);
primary_inputs.add(assign_map(gold_wire));
primary_inputs.add(assign_map(gate_wire));
primary_inputs.add(wire);
} }
else else
{ {
@ -283,6 +287,9 @@ struct EquivMakeWorker
if (!ct.cell_output(c->type, conn.first)) { if (!ct.cell_output(c->type, conn.first)) {
SigSpec old_sig = assign_map(conn.second); SigSpec old_sig = assign_map(conn.second);
SigSpec new_sig = rd_signal_map(old_sig); SigSpec new_sig = rd_signal_map(old_sig);
for (int i = 0; i < GetSize(old_sig); i++)
if (primary_inputs.check(old_sig[i]))
new_sig[i] = old_sig[i];
if (old_sig != new_sig) { if (old_sig != new_sig) {
log("Changing input %s of cell %s (%s): %s -> %s\n", log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type), log_id(conn.first), log_id(c), log_id(c->type),