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WIP docs: Proto log_help
Define `PrettyHelp` class with methods for declaring different parts of help message. Currently able to produce standard help messages as expected. Updates chformal to use (only) the new help_v2. Currently makes use of a global static to track the current help context, allowing register.h to live in blissful ignorance and instead rely on help_v2 implementations calling `auto *help = PrettyHelp::get_current();` and `return true;` to minimise impact on rebuilds (i.e. not requiring every source file to be recompiled).
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6 changed files with 241 additions and 175 deletions
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@ -19,6 +19,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/log_help.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -70,59 +71,59 @@ static bool is_triggered_check_cell(RTLIL::Cell * cell)
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}
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struct ChformalPass : public Pass {
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ChformalPass() : Pass("chformal", "change formal constraints of the design", {
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{
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.signature = "chformal [types] [mode] [options] [selection]",
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.description = "Make changes to the formal constraints of the design. The [types] options the type of "
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"constraint to operate on. If none of the following options are given, the command "
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"will operate on all constraint types:",
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.options = {
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{"-assert $assert cells, representing assert(...) constraints"
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"\n-assume $assume cells, representing assume(...) constraints"
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"\n-live $live cells, representing assert(s_eventually ...)"
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"\n-fair $fair cells, representing assume(s_eventually ...)"
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"\n-cover $cover cells, representing cover() statements", ""},
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{"Additionally chformal will operate on $check cells corresponding to the selected constraint "
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"types.", ""},
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}
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},
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{
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.description = "Exactly one of the following modes must be specified:",
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.options = {
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{"-remove",
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"remove the cells and thus constraints from the design"},
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{"-early",
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"bypass FFs that only delay the activation of a constraint. When inputs "
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"of the bypassed FFs do not remain stable between clock edges, this may "
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"result in unexpected behavior."
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},
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{"-delay <N>",
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"delay activation of the constraint by <N> clock cycles"
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},
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{"-skip <N>",
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"ignore activation of the constraint in the first <N> clock cycles"
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},
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{"-coverenable",
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"add cover statements for the enable signals of the constraints"
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ChformalPass() : Pass("chformal", "change formal constraints of the design") {}
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bool help_v2() override {
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auto *help = PrettyHelp::get_current();
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help->usage("chformal [types] [mode] [options] [selection]");
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help->paragraph(
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"Make changes to the formal constraints of the design. The [types] options "
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"the type of constraint to operate on. If none of the following options are "
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"given, the command will operate on all constraint types:"
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);
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help->optiongroup("[types]");
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help->option("-assert", "`$assert` cells, representing ``assert(...)`` constraints");
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help->option("-assume", "`$assume` cells, representing ``assume(...)`` constraints");
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help->option("-live", "`$live` cells, representing ``assert(s_eventually ...)``");
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help->option("-fair", "`$fair` cells, representing ``assume(s_eventually ...)``");
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help->option("-cover", "`$cover` cells, representing ``cover()`` statements");
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help->paragraph(
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"Additionally chformal will operate on `$check` cells corresponding to the "
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"selected constraint types."
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);
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help->endgroup();
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help->paragraph("Exactly one of the following modes must be specified:");
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help->optiongroup("[mode]");
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help->option("-remove", "remove the cells and thus constraints from the design");
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help->option("-early",
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"bypass FFs that only delay the activation of a constraint. When inputs "
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"of the bypassed FFs do not remain stable between clock edges, this may "
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"result in unexpected behavior."
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);
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help->option("-delay <N>", "delay activation of the constraint by <N> clock cycles");
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help->option("-skip <N>", "ignore activation of the constraint in the first <N> clock cycles");
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help->option("-coverenable",
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"add cover statements for the enable signals of the constraints"
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#ifdef YOSYS_ENABLE_VERIFIC
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"\n\nNote: For the Verific frontend it is currently not guaranteed that a "
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"reachable SVA statement corresponds to an active enable signal."
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"\n\n"
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"Note: For the Verific frontend it is currently not guaranteed that a "
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"reachable SVA statement corresponds to an active enable signal."
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#endif
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},
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{"-assert2assume"
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"\n-assume2assert"
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"\n-live2fair"
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"\n-fair2live",
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"change the roles of cells as indicated. these options can be combined"
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},
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{"-lower",
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"convert each $check cell into an $assert, $assume, $live, $fair or "
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"$cover cell. If the $check cell contains a message, also produce a "
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"$print cell."
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},
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}
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},
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}) { }
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);
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help->option("-assert2assume");
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help->option("-assume2assert");
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help->option("-live2fair");
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help->option("-fair2live", "change the roles of cells as indicated. these options can be combined");
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help->option("-lower",
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"convert each $check cell into an $assert, $assume, $live, $fair or "
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"$cover cell. If the $check cell contains a message, also produce a "
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"$print cell."
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);
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return true;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool assert2assume = false;
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