mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-10 09:15:49 +00:00
Code Activity

tests: check shifts by amounts that overflow int

Browse source
This commit is contained in:
George Rennie 2025-05-07 15:12:33 +02:00
parent 0dcd94b6ad
commit af933b4f38
1 changed files with 22 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

22
tests/opt/opt_expr_shift.ys
View file

@ -48,3 +48,25 @@ select -assert-none t:$shl
select -assert-none t:$shr select -assert-none t:$shr
select -assert-none t:$sshl select -assert-none t:$sshl
select -assert-none t:$sshr select -assert-none t:$sshr
design -reset
read_verilog <<EOT
module top (in, out1, out2);
input wire in;
output wire [7:0] out1;
output wire [7:0] out2;
assign out1 = (in >> 36'hfffffffff);
wire signed [35:0] shamt = 36'hfffffffff;
assign out2 = (in >> shamt);
endmodule
EOT
equiv_opt opt_expr
design -load postopt
select -assert-none t:$shl
select -assert-none t:$shr
select -assert-none t:$sshl
select -assert-none t:$sshr