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Fix tests

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This commit is contained in:
Miodrag Milanovic 2020-01-10 14:48:01 +01:00
parent 6888799c75
commit af852a0ea8
3 changed files with 11 additions and 12 deletions
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8
tests/arch/xilinx/add_sub.ys
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@ -4,8 +4,8 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 14 t:LUT2
select -assert-count 6 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
stat
select -assert-count 16 t:LUT2
select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:CARRY4 %% t:* %D