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xilinx_dsp_cascade to also cascade AREG and BREG

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This commit is contained in:
Eddie Hung 2019-09-26 13:29:18 -07:00
parent 832216dab0
commit af59856ba1
2 changed files with 176 additions and 458 deletions
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42
passes/pmgen/xilinx_dsp.cc
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@ -609,30 +609,26 @@ struct XilinxDspPass : public Pass {
for (auto module : design->selected_modules()) {
xilinx_simd_pack(module, module->selected_cells());
{
xilinx_dsp_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
}
// Separating out CREG packing is necessary since there
// is no guarantee that the cell ordering corresponds
// to the "expected" case (i.e. the order in which
// they appear in the source) thus the possiblity
// existed that a register got packed as CREG into a
// downstream DSP that should have otherwise been a
// PREG of an upstream DSP that had not been pattern
// matched yet
{
xilinx_dsp_CREG_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_packC(xilinx_dsp_packC);
}
do {
did_something = false;
{
xilinx_dsp_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
}
// Separating out CREG packing is necessary since there
// is no guarantee that the cell ordering corresponds
// to the "expected" case (i.e. the order in which
// they appear in the source) thus the possiblity
// existed that a register got packed as CREG into a
// downstream DSP that should have otherwise been a
// PREG of an upstream DSP that had not been pattern
// matched yet
{
xilinx_dsp_CREG_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_packC(xilinx_dsp_packC);
}
{
xilinx_dsp_cascade_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_cascadeP();
//pm.run_xilinx_dsp_cascadeAB();
break;
} while (did_something);
pm.run_xilinx_dsp_cascade();
}
}
}
} XilinxDspPass;