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xilinx_dsp_cascade to also cascade AREG and BREG
This commit is contained in:
Eddie Hung
parent
832216dab0
commit
af59856ba1
2 changed files with 176 additions and 458 deletions
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@ -609,30 +609,26 @@ struct XilinxDspPass : public Pass {
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for (auto module : design->selected_modules()) {
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xilinx_simd_pack(module, module->selected_cells());
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{
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xilinx_dsp_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
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}
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// Separating out CREG packing is necessary since there
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// is no guarantee that the cell ordering corresponds
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// to the "expected" case (i.e. the order in which
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// they appear in the source) thus the possiblity
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// existed that a register got packed as CREG into a
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// downstream DSP that should have otherwise been a
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// PREG of an upstream DSP that had not been pattern
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// matched yet
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{
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xilinx_dsp_CREG_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_packC(xilinx_dsp_packC);
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}
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do {
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did_something = false;
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{
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xilinx_dsp_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
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}
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// Separating out CREG packing is necessary since there
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// is no guarantee that the cell ordering corresponds
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// to the "expected" case (i.e. the order in which
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// they appear in the source) thus the possiblity
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// existed that a register got packed as CREG into a
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// downstream DSP that should have otherwise been a
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// PREG of an upstream DSP that had not been pattern
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// matched yet
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{
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xilinx_dsp_CREG_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_packC(xilinx_dsp_packC);
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}
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{
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xilinx_dsp_cascade_pm pm(module, module->selected_cells());
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pm.run_xilinx_dsp_cascadeP();
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//pm.run_xilinx_dsp_cascadeAB();
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break;
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} while (did_something);
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pm.run_xilinx_dsp_cascade();
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}
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}
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}
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} XilinxDspPass;
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@ -1,6 +1,19 @@
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pattern xilinx_dsp_cascadeP
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pattern xilinx_dsp_cascade
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udata <vector<std::pair<Cell*,bool>>> chain longest_chain
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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udata <vector<std::tuple<Cell*,int,int,int>>> chain longest_chain
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state <Cell*> next
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state <SigSpec> clock
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state <int> AREG BREG
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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code
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#define MAX_DSP_CASCADE 20
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@ -14,41 +27,71 @@ endmatch
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code
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longest_chain.clear();
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chain.emplace_back(first, false);
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chain.emplace_back(first, -1, -1, -1);
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subpattern(tail);
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finally
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chain.pop_back();
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log_assert(chain.empty());
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if (GetSize(longest_chain) > 1) {
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Cell *dsp = longest_chain.front().first;
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Cell *dsp = std::get<0>(longest_chain.front());
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Cell *dsp_pcin;
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int P, AREG, BREG;
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for (int i = 1; i < GetSize(longest_chain); i++) {
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Cell *dsp_pcin = longest_chain[i].first;
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bool shift17 = longest_chain[i].second;
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std::tie(dsp_pcin,P,AREG,BREG) = longest_chain[i];
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dsp_pcin->setPort(ID(C), Const(0, 48));
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if (i % MAX_DSP_CASCADE > 0) {
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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if (P >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
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if (shift17)
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opmode[6] = State::S1;
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else
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opmode[6] = State::S0;
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SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
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if (P == 17)
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opmode[6] = State::S1;
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else if (P == 0)
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opmode[6] = State::S0;
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else log_abort();
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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dsp_pcin->setPort(\OPMODE, opmode);
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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dsp_pcin->setPort(\OPMODE, opmode);
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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if (AREG >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 30);
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dsp_pcin->setPort(ID(ACIN), cascade);
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dsp->setPort(ID(ACOUT), cascade);
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dsp_pcin->unsetPort(ID(A));
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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dsp->setParam(ID(ACASCREG), AREG);
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dsp_pcin->setParam(ID(A_INPUT), Const("CASCADE"));
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log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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if (BREG >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 18);
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dsp_pcin->setPort(ID(BCIN), cascade);
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dsp->setPort(ID(BCOUT), cascade);
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dsp_pcin->unsetPort(ID(B));
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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dsp->setParam(ID(BCASCREG), BREG);
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dsp_pcin->setParam(ID(B_INPUT), Const("CASCADE"));
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log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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}
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else {
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log_debug("Blocking PCOUT -> PCIN cascade for %s -> %s (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
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log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
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}
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dsp = dsp_pcin;
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@ -63,35 +106,35 @@ endcode
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subpattern tail
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arg first
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arg next
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match next
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select next->type.in(\DSP48E1)
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select !param(next, \CREG, State::S1).as_bool()
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select port(next, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(next, \C, SigSpec())) > 1
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select nusers(port(next, \PCIN, SigSpec())) == 0
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index <SigBit> port(next, \C)[0] === port(chain.back().first, \P)[0]
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match nextP
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select nextP->type.in(\DSP48E1)
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select !param(nextP, \CREG, State::S1).as_bool()
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select port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(nextP, \C, SigSpec())) > 1
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select nusers(port(nextP, \PCIN, SigSpec())) == 0
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index <SigBit> port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[0]
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semioptional
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endmatch
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match next_shift17
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if !next_shift17
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select next_shift17->type.in(\DSP48E1)
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select !param(next_shift17, \CREG, State::S1).as_bool()
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select port(next_shift17, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(next_shift17, \C, SigSpec())) > 1
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select nusers(port(next_shift17, \PCIN, SigSpec())) == 0
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index <SigBit> port(next_shift17, \C)[0] === port(chain.back().first, \P)[17]
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match nextP_shift17
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if !nextP
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select nextP_shift17->type.in(\DSP48E1)
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select !param(nextP_shift17, \CREG, State::S1).as_bool()
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select port(nextP_shift17, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(nextP_shift17, \C, SigSpec())) > 1
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select nusers(port(nextP_shift17, \PCIN, SigSpec())) == 0
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index <SigBit> port(nextP_shift17, \C)[0] === port(std::get<0>(chain.back()), \P)[17]
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semioptional
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endmatch
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code next
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if (!next)
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next = next_shift17;
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next = nextP;
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if (!nextP)
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next = nextP_shift17;
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if (next) {
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chain.emplace_back(next, next_shift17);
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auto unextend = [](const SigSpec &sig) {
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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@ -101,17 +144,82 @@ code next
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++i;
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return sig.extract(0, i);
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};
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}
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endcode
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code argQ clock AREG
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AREG = 0;
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if (next) {
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Cell *prev = std::get<0>(chain.back());
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if (param(prev, \AREG, 2).as_int() > 0 &&
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param(next, \AREG, 2).as_int() > 0 &&
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param(next, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" &&
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port(next, \ACIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \ACOUT, SigSpec())) <= 1) {
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argQ = unextend(port(next, \A));
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dffrstmux && port(prev, \RSTA, State::S0) != State::S0)
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goto reject_AREG;
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if (dffrstmux && port(dffrstmux, \S) != port(prev, \RSTA, State::S0))
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goto reject_AREG;
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if (!dffcemux && port(prev, \CEA2, State::S0) != State::S0)
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goto reject_AREG;
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if (dffcemux && port(dffcemux, \S) != port(prev, \CEA2, State::S0))
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goto reject_AREG;
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if (dffD == unextend(port(prev, \A)))
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AREG = 1;
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reject_AREG: ;
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}
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}
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}
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endcode
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code argQ clock BREG
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BREG = 0;
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if (next) {
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Cell *prev = std::get<0>(chain.back());
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if (param(prev, \BREG, 2).as_int() > 0 &&
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param(next, \BREG, 2).as_int() > 0 &&
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param(next, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT" &&
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port(next, \BCIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \BCOUT, SigSpec())) <= 1) {
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argQ = unextend(port(next, \B));
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dffrstmux && port(prev, \RSTB, State::S0) != State::S0)
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goto reject_BREG;
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if (dffrstmux && port(dffrstmux, \S) != port(prev, \RSTB, State::S0))
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goto reject_BREG;
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if (!dffcemux && port(prev, \CEB2, State::S0) != State::S0)
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goto reject_BREG;
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if (dffcemux && port(dffcemux, \S) != port(prev, \CEB2, State::S0))
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goto reject_BREG;
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if (dffD == unextend(port(prev, \B)))
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BREG = 1;
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reject_BREG: ;
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}
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}
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}
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endcode
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code
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if (next) {
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chain.emplace_back(next, nextP_shift17 ? 17 : nextP ? 0 : -1, AREG, BREG);
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SigSpec sigC = unextend(port(next, \C));
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// TODO: Cannot use 'reject' since semioptional
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if (next_shift17) {
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if (GetSize(sigC)+17 <= GetSize(port(chain.back().first, \P)) &&
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port(chain.back().first, \P).extract(17, GetSize(sigC)) != sigC)
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if (nextP_shift17) {
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if (GetSize(sigC)+17 <= GetSize(port(std::get<0>(chain.back()), \P)) &&
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port(std::get<0>(chain.back()), \P).extract(17, GetSize(sigC)) != sigC)
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subpattern(tail);
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}
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else {
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if (GetSize(sigC) <= GetSize(port(chain.back().first, \P)) &&
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port(chain.back().first, \P).extract(0, GetSize(sigC)) != sigC)
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if (GetSize(sigC) <= GetSize(port(std::get<0>(chain.back()), \P)) &&
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port(std::get<0>(chain.back()), \P).extract(0, GetSize(sigC)) != sigC)
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subpattern(tail);
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}
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@ -124,395 +232,6 @@ finally
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chain.pop_back();
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endcode
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// ##########
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pattern xilinx_dsp_cascadeAB
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state <SigBit> clock
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state <SigSpec> sigA sigB
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state <bool> ffA1cepol ffA2cepol ffB1cepol ffB2cepol
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state <bool> ffArstpol ffBrstpol
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state <Cell*> ffA1 ffA1cemux ffA1rstmux ffA2 ffA2cemux ffA2rstmux
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state <Cell*> ffB1 ffB1cemux ffB1rstmux ffB2 ffB2cemux ffB2rstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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match dspD
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select dspD->type.in(\DSP48E1)
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select (param(dspD, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \A, SigSpec())) > 1 && nusers(port(dspD, \ACIN, SigSpec())) == 0) || (param(dspD, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT" && nusers(port(dspD, \B, SigSpec())) > 1 && nusers(port(dspD, \BCIN, SigSpec())) == 0)
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endmatch
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code sigA sigB
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auto unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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if (param(dspD, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT")
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sigA = unextend(port(dspD, \A));
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if (param(dspD, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT")
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sigB = unextend(port(dspD, \B));
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endcode
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code argQ ffA2 ffA2cemux ffA2rstmux ffA2cepol ffArstpol ffA1 ffA1cemux ffA1rstmux ffA1cepol sigA clock
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if (!sigA.empty()) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA2 = dff;
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clock = dffclock;
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if (dffrstmux) {
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ffA2rstmux = dffrstmux;
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ffArstpol = dffrstpol;
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}
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if (dffcemux) {
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ffA2cemux = dffcemux;
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ffA2cepol = dffcepol;
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}
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sigA = dffD;
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// Now attempt to match A1
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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if ((ffA2rstmux != nullptr) ^ (dffrstmux != nullptr))
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goto reject_ffA1;
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if (dffrstmux) {
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if (ffArstpol != dffrstpol)
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goto reject_ffA1;
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if (port(ffA2rstmux, \S) != port(dffrstmux, \S))
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goto reject_ffA1;
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ffA1rstmux = dffrstmux;
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}
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ffA1 = dff;
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clock = dffclock;
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if (dffcemux) {
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ffA1cemux = dffcemux;
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ffA1cepol = dffcepol;
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}
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sigA = dffD;
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reject_ffA1: ;
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}
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}
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}
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endcode
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match dspQA2
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if ffA1
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select dspQA2->type.in(\DSP48E1)
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select param(dspQA2, \A_REG, 2).as_int() == 2
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select nusers(port(dspQA2, \A, SigSpec())) > 1
|
||||
select nusers(port(dspQA2, \ACOUT, SigSpec())) == 0
|
||||
slice offset GetSize(port(dspQA2, \A))
|
||||
index <SigBit> port(dspQA2, \A)[offset] === sigA[0]
|
||||
index <SigBit> port(dspQA2, \CLK, State::S0) === port(dspD, \CLK, State::S0)
|
||||
|
||||
// Check that the rest of sigA is present
|
||||
filter GetSize(port(dspQA2, \A)) >= offset + GetSize(sigA)
|
||||
filter port(dspQA2, \A).extract(offset, GetSize(sigA)) == sigA
|
||||
|
||||
optional
|
||||
endmatch
|
||||
|
||||
code
|
||||
if (dspQA2) {
|
||||
// Check CE and RST are compatible
|
||||
if ((ffA1cemux != nullptr) == port(dspQA2, \CEA1, State::S1).is_fully_const())
|
||||
reject;
|
||||
if ((ffA2cemux != nullptr) == port(dspQA2, \CEA2, State::S1).is_fully_const())
|
||||
reject;
|
||||
if ((ffA1rstmux != nullptr) == port(dspQA2, \RSTA, State::S0).is_fully_const())
|
||||
reject;
|
||||
if ((ffA2rstmux != nullptr) == port(dspQA2, \RSTA, State::S0).is_fully_const())
|
||||
reject;
|
||||
|
||||
if (ffA1cemux) {
|
||||
if (port(dspQA2, \CEA1) != port(ffA1cemux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffA1cepol)
|
||||
reject;
|
||||
}
|
||||
if (ffA2cemux) {
|
||||
if (port(dspQA2, \CEA2) != port(ffA2cemux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffA2cepol)
|
||||
reject;
|
||||
}
|
||||
if (ffA1rstmux) {
|
||||
if (port(dspQA2, \RSTA) != port(ffA1rstmux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffArstpol)
|
||||
reject;
|
||||
}
|
||||
if (ffA2rstmux) {
|
||||
if (port(dspQA2, \RSTA) != port(ffA2rstmux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffArstpol)
|
||||
reject;
|
||||
}
|
||||
}
|
||||
endcode
|
||||
|
||||
match dspQA1
|
||||
if !dspQA1 && !ffA1
|
||||
if ffA2
|
||||
select dspQA1->type.in(\DSP48E1)
|
||||
select param(dspQA1, \A_REG, 2).as_int() == 1
|
||||
select nusers(port(dspQA1, \A, SigSpec())) > 1
|
||||
select nusers(port(dspQA1, \ACOUT, SigSpec())) == 0
|
||||
slice offset GetSize(port(dspQA1, \A))
|
||||
index <SigBit> port(dspQA1, \A)[offset] === sigA[0]
|
||||
index <SigBit> port(dspQA1, \CLK, State::S0) === port(dspD, \CLK, State::S0)
|
||||
|
||||
// Check that the rest of sigA is present
|
||||
filter GetSize(port(dspQA1, \A)) >= offset + GetSize(sigA)
|
||||
filter port(dspQA1, \A).extract(offset, GetSize(sigA)) == sigA
|
||||
|
||||
optional
|
||||
endmatch
|
||||
|
||||
code
|
||||
if (dspQA1) {
|
||||
// Check CE and RST are compatible
|
||||
if ((ffA2cemux != NULL) == port(dspQA1, \CEA2, State::S1).is_fully_const())
|
||||
reject;
|
||||
if ((ffA2rstmux != NULL) == port(dspQA1, \RSTA, State::S0).is_fully_const())
|
||||
reject;
|
||||
|
||||
if (!ffA2cepol || !ffArstpol)
|
||||
reject;
|
||||
|
||||
if (ffA2cemux) {
|
||||
if (port(dspQA1, \CEA2) != port(ffA2cemux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffA2cepol)
|
||||
reject;
|
||||
}
|
||||
if (ffA2rstmux) {
|
||||
if (port(dspQA1, \RSTA) != port(ffA2rstmux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffArstpol)
|
||||
reject;
|
||||
}
|
||||
}
|
||||
endcode
|
||||
|
||||
code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol ffB1 ffB1cemux ffB1rstmux ffB1cepol sigB clock
|
||||
if (!sigB.empty()) {
|
||||
argQ = sigB;
|
||||
subpattern(in_dffe);
|
||||
if (dff) {
|
||||
ffB2 = dff;
|
||||
clock = dffclock;
|
||||
if (dffrstmux) {
|
||||
ffB2rstmux = dffrstmux;
|
||||
ffBrstpol = dffrstpol;
|
||||
}
|
||||
if (dffcemux) {
|
||||
ffB2cemux = dffcemux;
|
||||
ffB2cepol = dffcepol;
|
||||
}
|
||||
sigB = dffD;
|
||||
|
||||
// Now attempt to match B1
|
||||
argQ = sigB;
|
||||
subpattern(in_dffe);
|
||||
if (dff) {
|
||||
if ((ffB2rstmux != nullptr) ^ (dffrstmux != nullptr))
|
||||
goto reject_ffB1;
|
||||
if (dffrstmux) {
|
||||
if (ffBrstpol != dffrstpol)
|
||||
goto reject_ffB1;
|
||||
if (port(ffB2rstmux, \S) != port(dffrstmux, \S))
|
||||
goto reject_ffB1;
|
||||
ffB1rstmux = dffrstmux;
|
||||
}
|
||||
|
||||
ffB1 = dff;
|
||||
clock = dffclock;
|
||||
|
||||
if (dffcemux) {
|
||||
ffB1cemux = dffcemux;
|
||||
ffB1cepol = dffcepol;
|
||||
}
|
||||
sigB = dffD;
|
||||
|
||||
reject_ffB1: ;
|
||||
}
|
||||
}
|
||||
}
|
||||
endcode
|
||||
|
||||
match dspQB2
|
||||
if ffB1
|
||||
select dspQB2->type.in(\DSP48E1)
|
||||
select param(dspQB2, \B_REG, 2).as_int() == 2
|
||||
select nusers(port(dspQB2, \B, SigSpec())) > 1
|
||||
select nusers(port(dspQB2, \BCOUT, SigSpec())) == 0
|
||||
slice offset GetSize(port(dspQB2, \B))
|
||||
index <SigBit> port(dspQB2, \B)[offset] === sigB[0]
|
||||
index <SigBit> port(dspQB2, \CLK, State::S0) === port(dspD, \CLK, State::S0)
|
||||
|
||||
// Check that the rest of sigB is present
|
||||
filter GetSize(port(dspQB2, \B)) >= offset + GetSize(sigB)
|
||||
filter port(dspQB2, \B).extract(offset, GetSize(sigB)) == sigB
|
||||
|
||||
optional
|
||||
endmatch
|
||||
|
||||
code
|
||||
if (dspQB2) {
|
||||
// Check CE and RST are compatible
|
||||
if ((ffB1cemux != nullptr) == port(dspQB2, \CEB1, State::S1).is_fully_const())
|
||||
reject;
|
||||
if ((ffB2cemux != NULL) == port(dspQB2, \CEB2, State::S1).is_fully_const())
|
||||
reject;
|
||||
if ((ffB1rstmux != NULL) == port(dspQB2, \RSTB, State::S0).is_fully_const())
|
||||
reject;
|
||||
if ((ffB2rstmux != NULL) == port(dspQB2, \RSTB, State::S0).is_fully_const())
|
||||
reject;
|
||||
|
||||
if (ffB1cemux) {
|
||||
if (port(dspQB2, \CEB1) != port(ffB1cemux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffB1cepol)
|
||||
reject;
|
||||
}
|
||||
if (ffB2cemux) {
|
||||
if (port(dspQB2, \CEB2) != port(ffB2cemux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffB2cepol)
|
||||
reject;
|
||||
}
|
||||
if (ffB2rstmux) {
|
||||
if (port(dspQB2, \RSTB) != port(ffB2rstmux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffBrstpol)
|
||||
reject;
|
||||
}
|
||||
}
|
||||
endcode
|
||||
|
||||
match dspQB1
|
||||
if !dspQB1 && !ffB1
|
||||
if ffB2
|
||||
select dspQB1->type.in(\DSP48E1)
|
||||
select param(dspQB1, \B_REG, 2).as_int() >= 1
|
||||
select nusers(port(dspQB1, \B, SigSpec())) > 1
|
||||
select nusers(port(dspQB1, \BCOUT, SigSpec())) == 0
|
||||
slice offset GetSize(port(dspQB1, \B))
|
||||
index <SigBit> port(dspQB1, \B)[offset] === sigB[0]
|
||||
index <SigBit> port(dspQB1, \CLK, State::S0) === port(dspD, \CLK, State::S0)
|
||||
|
||||
// Check that the rest of sigB is present
|
||||
filter GetSize(port(dspQB1, \B)) >= offset + GetSize(sigB)
|
||||
filter port(dspQB1, \B).extract(offset, GetSize(sigB)) == sigB
|
||||
|
||||
optional
|
||||
endmatch
|
||||
|
||||
code
|
||||
if (dspQB1) {
|
||||
// Check CE and RST are compatible
|
||||
if ((ffB2cemux != NULL) != port(dspQB1, \CEB2, State::S1).is_fully_const())
|
||||
reject;
|
||||
if ((ffB2rstmux != NULL) != port(dspQB1, \RSTB, State::S0).is_fully_const())
|
||||
reject;
|
||||
|
||||
if (!ffA2cepol || !ffArstpol)
|
||||
reject;
|
||||
|
||||
if (ffA2cemux) {
|
||||
if (port(dspQB1, \CEB2) != port(ffB2cemux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffA2cepol)
|
||||
reject;
|
||||
}
|
||||
if (ffA2rstmux) {
|
||||
if (port(dspQB1, \RSTB) != port(ffB2rstmux, \S))
|
||||
reject;
|
||||
// TODO: Support inversions
|
||||
if (!ffArstpol)
|
||||
reject;
|
||||
}
|
||||
}
|
||||
endcode
|
||||
|
||||
code
|
||||
if (dspQA1 || dspQA2) {
|
||||
dspD->setParam(\A_INPUT, Const("CASCADE"));
|
||||
dspD->setPort(\A, Const(0, 30));
|
||||
|
||||
Wire *cascade = module->addWire(NEW_ID, 30);
|
||||
if (dspQA1) {
|
||||
dspQA1->setParam(\ACASCREG, 1);
|
||||
dspQA1->setPort(\ACOUT, cascade);
|
||||
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dspQA1), log_id(dspD));
|
||||
}
|
||||
else if (dspQA2) {
|
||||
dspQA2->setParam(\ACASCREG, 2);
|
||||
dspQA2->setPort(\ACOUT, cascade);
|
||||
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dspQA2), log_id(dspD));
|
||||
}
|
||||
else
|
||||
log_abort();
|
||||
|
||||
dspD->setPort(\ACIN, cascade);
|
||||
did_something = true;
|
||||
}
|
||||
if (dspQB1 || dspQB2) {
|
||||
dspD->setParam(\B_INPUT, Const("CASCADE"));
|
||||
dspD->setPort(\B, Const(0, 18));
|
||||
|
||||
Wire *cascade = module->addWire(NEW_ID, 18);
|
||||
if (dspQB1) {
|
||||
dspQB1->setParam(\BCASCREG, 1);
|
||||
dspQB1->setPort(\BCOUT, cascade);
|
||||
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dspQB1), log_id(dspD));
|
||||
}
|
||||
else if (dspQB2) {
|
||||
dspQB2->setParam(\BCASCREG, 2);
|
||||
dspQB2->setPort(\BCOUT, cascade);
|
||||
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dspQB2), log_id(dspD));
|
||||
}
|
||||
else
|
||||
log_abort();
|
||||
|
||||
dspD->setPort(\BCIN, cascade);
|
||||
did_something = true;
|
||||
}
|
||||
|
||||
accept;
|
||||
endcode
|
||||
|
||||
|
||||
// #######################
|
||||
|
||||
subpattern in_dffe
|
||||
|
|
@ -525,6 +244,9 @@ code
|
|||
reject;
|
||||
if (c.wire->get_bool_attribute(\keep))
|
||||
reject;
|
||||
Const init = c.wire->attributes.at(\init, State::Sx);
|
||||
if (!init.is_fully_undef() && !init.is_fully_zero())
|
||||
reject;
|
||||
}
|
||||
endcode
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue