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Merge branch 'main' into emil/turbo-celltypes

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nella 2026-02-28 18:40:38 +01:00 • committed by GitHub
commit af56efaa83
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11 changed files with 167 additions and 135 deletions
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1
tests/arch/ice40/ice40_dsp_const.ys
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@ -74,6 +74,7 @@ EOT
techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
async2sync
equiv_make top ref equiv
select -assert-any -module equiv t:$equiv
equiv_induct

2
tests/opt/opt_hier.tcl
View file

@ -27,7 +27,7 @@ foreach fn [glob opt_hier_*.v] {
design -copy-from gate -as gate A:top
yosys rename -hide
equiv_make gold gate equiv
equiv_induct equiv
equiv_induct -ignore-unknown-cells equiv
equiv_status -assert equiv
log -pop

4
tests/various/specify.ys
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@ -43,7 +43,7 @@ select n:C_* -assert-count 2
equiv_make gold gate equiv
hierarchy -top equiv
equiv_struct
equiv_induct -seq 5
equiv_induct -ignore-unknown-cells -seq 5
equiv_status -assert
design -reset
@ -57,7 +57,7 @@ select n:B_* -assert-count 2
equiv_make gold gate equiv
hierarchy -top equiv
equiv_struct
equiv_induct -seq 5
equiv_induct -ignore-unknown-cells -seq 5
equiv_status -assert
design -reset