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ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set

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Eddie Hung 2019-04-19 21:09:55 -07:00
parent 59c993e437
commit af4652522f
2 changed files with 7 additions and 4 deletions
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2
techlibs/ice40/synth_ice40.cc
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@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}