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Add blackbox model for $__ABC9_FF_ so that clock partitioning works
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@ -30,6 +30,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
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: (S0 ? I1 : I0);
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: (S0 ? I1 : I0);
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endmodule
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endmodule
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module \$__ABC9_FF_ (input D, output Q);
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endmodule
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(* abc_box_id = 1000 *)
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(* abc_box_id = 1000 *)
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module \$__ABC9_ASYNC (input A, S, output Y);
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module \$__ABC9_ASYNC (input A, S, output Y);
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endmodule
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endmodule
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