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sv: Add support for memories of a typedef

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-09-20 11:46:37 +01:00
parent 30d2326030
commit af25585170
2 changed files with 30 additions and 6 deletions
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10
tests/svtypes/typedef_memory_2.sv Normal file
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module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
typedef logic [3:0] nibble;
nibble mem[0:15];
always @(posedge clk) begin
if (wen) mem[addr] <= wdata;
rdata <= mem[addr];
end
endmodule