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Tests for ram_style = "huge"

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iCE40 SPRAM and Xilinx URAM
This commit is contained in:
KrystalDelusion 2022-07-07 10:27:54 +12:00
parent de2f140c09
commit af1b9c9e07
4 changed files with 219 additions and 0 deletions
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22
tests/arch/ice40/spram.v Normal file
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module top (clk, write_enable, read_enable, write_data, addr, read_data);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter SKIP_RDEN = 1;
input clk;
input write_enable, read_enable;
input [DATA_WIDTH - 1 : 0] write_data;
input [ADDR_WIDTH - 1 : 0] addr;
output [DATA_WIDTH - 1 : 0] read_data;
(* ram_style = "huge" *)
reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
always @(posedge clk) begin
if (write_enable)
mem[addr] <= write_data;
else if (SKIP_RDEN || read_enable)
read_data <= mem[addr];
end
endmodule

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tests/arch/ice40/spram.ys Normal file
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read_verilog spram.v
hierarchy -top top
synth_ice40
select -assert-count 1 t:SB_SPRAM256KA
select -assert-none t:SB_SPRAM256KA %% t:* %D
# Testing with pattern as described in pattern document
design -reset
read_verilog spram.v
chparam -set SKIP_RDEN 0
hierarchy -top top
synth_ice40
select -assert-count 1 t:SB_SPRAM256KA
# Below fails due to extra SB_LUT4
# select -assert-none t:SB_SPRAM256KA %% t:* %D