mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-11 13:40:53 +00:00
Code Activity

Address SigBit/SigSpec confusion issues under c++20

Browse source
This commit is contained in:
Martin Povišer 2024-02-08 17:46:00 +01:00
parent 0cdd4273b4
commit af1a5cfeb9
9 changed files with 19 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/pmgen/xilinx_dsp_CREG.pmg
View file

@ -135,7 +135,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ