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Address SigBit/SigSpec confusion issues under c++20

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This commit is contained in:
Martin Povišer 2024-02-08 17:46:00 +01:00
parent 0cdd4273b4
commit af1a5cfeb9
9 changed files with 19 additions and 14 deletions
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4
passes/pmgen/ice40_dsp.pmg
View file

@ -346,7 +346,7 @@ endmatch
code argQ argD
{
if (clock != SigBit()) {
if (port(ff, \CLK) != clock)
if (port(ff, \CLK)[0] != clock)
reject;
if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
reject;
@ -393,7 +393,7 @@ endmatch
code argQ
if (ff) {
if (clock != SigBit()) {
if (port(ff, \CLK) != clock)
if (port(ff, \CLK)[0] != clock)
reject;
if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
reject;

4
passes/pmgen/xilinx_dsp.pmg
View file

@ -415,7 +415,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ
@ -465,7 +465,7 @@ match ff
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ

4
passes/pmgen/xilinx_dsp48a.pmg
View file

@ -354,7 +354,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ
@ -404,7 +404,7 @@ match ff
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ

2
passes/pmgen/xilinx_dsp_CREG.pmg
View file

@ -135,7 +135,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ

4
passes/pmgen/xilinx_dsp_cascade.pmg
View file

@ -46,7 +46,7 @@ pattern xilinx_dsp_cascade
udata <std::function<SigSpec(const SigSpec&)>> unextend
udata <vector<std::tuple<Cell*,int,int,int>>> chain longest_chain
state <Cell*> next
state <SigSpec> clock
state <SigBit> clock
state <int> AREG BREG
// Variables used for subpatterns
@ -395,7 +395,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ