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ast, read_verilog: ownership in AST, use C++ styles for parser and lexer

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This commit is contained in:
Emil J. Tywoniak 2025-05-21 12:14:50 +02:00
parent 6900818105
commit af0bab9fc7
22 changed files with 2496 additions and 2615 deletions
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2
tests/sat/alu.v
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@ -1,4 +1,4 @@
module alu(
module alu (
input clk,
input [7:0] A,
input [7:0] B,

2
tests/various/svalways.sh
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@ -27,7 +27,7 @@ always_comb @(d)
endmodule
EOT
) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null
) 2>&1 | grep -F "ERROR: syntax error, unexpected @" > /dev/null
# Incorrect use of always_comb
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT

2
tests/verilog/bug2042-sv.ys
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@ -48,7 +48,7 @@ sat -verify -prove-asserts
design -reset
logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ;" 1
read_verilog -sv <<EOT
module Task_Test_Top
(

2
tests/verilog/task_attr.ys
View file

@ -15,7 +15,7 @@ EOT
select -assert-none a:* a:src %d
logger -expect error "syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT" 1
logger -expect error "syntax error, unexpected ;, expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT" 1
design -reset
read_verilog <<EOT
module top;