3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-17 19:36:18 +00:00

ast, read_verilog: ownership in AST, use C++ styles for parser and lexer

This commit is contained in:
Emil J. Tywoniak 2025-05-21 12:14:50 +02:00
parent 6900818105
commit af0bab9fc7
22 changed files with 2496 additions and 2615 deletions

View file

@ -1292,7 +1292,7 @@ struct RTLIL::Design
dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<RTLIL::Binding*> bindings_;
std::vector<AST::AstNode*> verilog_packages, verilog_globals;
std::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;
std::unique_ptr<define_map_t> verilog_defines;
std::vector<RTLIL::Selection> selection_stack;