mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-18 20:03:39 +00:00
Code Activity

ast, read_verilog: ownership in AST, use C++ styles for parser and lexer

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-21 12:14:50 +02:00
parent 6900818105
commit af0bab9fc7
22 changed files with 2496 additions and 2615 deletions
Download patch file Download diff file Expand all files Collapse all files

12
kernel/rtlil.cc
View file

@ -920,10 +920,6 @@ RTLIL::Design::~Design()
delete pr.second;
for (auto n : bindings_)
delete n;
for (auto n : verilog_packages)
delete n;
for (auto n : verilog_globals)
delete n;
#ifdef WITH_PYTHON
RTLIL::Design::get_all_designs()->erase(hashidx_);
#endif
@ -5649,12 +5645,12 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
cover("kernel.rtlil.sigspec.parse.const");
AST::get_line_num = sigspec_parse_get_dummy_line_num;
AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
if (ast == NULL)
// TODO fix
// AST::get_line_num = sigspec_parse_get_dummy_line_num;
auto ast = VERILOG_FRONTEND::const2ast(netname);
if (ast == nullptr)
return false;
sig.append(RTLIL::Const(ast->bits));
delete ast;
continue;
}