mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Code Activity

Tidying TODOs

Browse source
This commit is contained in:
Krystine Sherwin 2023-12-08 09:46:02 +13:00
parent 1e3b90ae56
commit aef9921fc9
No known key found for this signature in database
5 changed files with 25 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/source/yosys_internals/flow/verilog_frontend.rst
View file

@ -409,9 +409,7 @@ multiplexers.
In more complex examples (e.g. asynchronous resets) the part of the
``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree that describes the asynchronous
reset must first be transformed to the correct ``RTLIL::SyncRule`` objects. This
is done by the ``proc_adff`` pass.
.. todo:: The ``proc_adff`` pass doesn't exist anymore?
is done by the ``proc_arst`` pass.
The ProcessGenerator algorithm
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~