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https://github.com/YosysHQ/yosys
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43 changed files with 258 additions and 27 deletions
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@ -24,9 +24,11 @@
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module _80_xilinx_lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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(* force_downto *)
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input [WIDTH-1:0] P, G;
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input CI;
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(* force_downto *)
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output [WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = WIDTH <= 2;
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@ -41,7 +43,9 @@ module _80_xilinx_lcu (P, G, CI, CO);
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generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin
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(* force_downto *)
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wire [WIDTH-1:0] C = {CO, CI};
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(* force_downto *)
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wire [WIDTH-1:0] S = P & ~G;
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generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
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@ -59,8 +63,11 @@ end else begin
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
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(* force_downto *)
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wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] C;
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assign CO = C;
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@ -103,20 +110,27 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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genvar i;
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@ -129,7 +143,9 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
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generate if (`LUT_SIZE == 4) begin
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(* force_downto *)
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wire [Y_WIDTH-1:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH-1:0] S = {AA ^ BB};
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genvar i;
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@ -149,6 +165,7 @@ generate if (`LUT_SIZE == 4) begin
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end else if (EXPLICIT_CARRY) begin
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(* force_downto *)
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wire [Y_WIDTH-1:0] S = AA ^ BB;
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wire CINIT;
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@ -161,7 +178,9 @@ end else if (EXPLICIT_CARRY) begin
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// So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
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// e.g. off fabric dedicated chain. CO is the carry outputs that are
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// available to the fabric.
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(* force_downto *)
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wire [Y_WIDTH-1:0] CO_CHAIN;
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(* force_downto *)
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wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
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// If carry chain is being initialized to a constant, techmap the constant
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@ -250,10 +269,14 @@ end else begin
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localparam MAX_WIDTH = CARRY4_COUNT * 4;
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localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
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(* force_downto *)
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wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};
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(* force_downto *)
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wire [MAX_WIDTH-1:0] O;
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(* force_downto *)
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wire [MAX_WIDTH-1:0] C;
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assign Y = O, CO = C;
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