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commit
aee439360b
43 changed files with 258 additions and 27 deletions
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@ -57,8 +57,11 @@ module _80_mul (A, B, Y);
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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@ -119,13 +122,19 @@ module _80_mul (A, B, Y);
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localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
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localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
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if (A_SIGNED && B_SIGNED) begin
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(* force_downto *)
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire signed [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire signed [Y_WIDTH-1:0] partial_sum [n:0];
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end
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else begin
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(* force_downto *)
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire [Y_WIDTH-1:0] partial_sum [n:0];
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end
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@ -170,13 +179,19 @@ module _80_mul (A, B, Y);
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localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
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localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
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if (A_SIGNED && B_SIGNED) begin
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(* force_downto *)
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wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire signed [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire signed [Y_WIDTH-1:0] partial_sum [n:0];
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end
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else begin
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(* force_downto *)
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wire [partial_Y_WIDTH-1:0] partial [n-1:0];
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(* force_downto *)
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wire [last_Y_WIDTH-1:0] last_partial;
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(* force_downto *)
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wire [Y_WIDTH-1:0] partial_sum [n:0];
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end
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@ -249,8 +264,11 @@ module _90_soft_mul (A, B, Y);
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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// Indirection necessary since mapping
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