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Clifford Wolf 2014-02-16 14:32:56 +01:00
parent 9c29969bbc
commit aeb36b0b8b
6 changed files with 74 additions and 3 deletions
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15
manual/PRESENTATION_ExAdv/sym_mul_map.v Normal file
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module \$mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
endmodule