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Progress in presentation

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This commit is contained in:
Clifford Wolf 2014-02-16 14:32:56 +01:00
parent 9c29969bbc
commit aeb36b0b8b
6 changed files with 74 additions and 3 deletions
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5
manual/PRESENTATION_ExAdv/Makefile
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@ -1,5 +1,5 @@
all: select_01.pdf red_or3x1.pdf
all: select_01.pdf red_or3x1.pdf sym_mul.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
@ -7,3 +7,6 @@ select_01.pdf: select_01.v select_01.ys
red_or3x1.pdf: red_or3x1_*
../../yosys red_or3x1_test.ys
sym_mul.pdf: sym_mul_*
../../yosys sym_mul_test.ys

6
manual/PRESENTATION_ExAdv/sym_mul_cells.v Normal file
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module MYMUL(A, B, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y;
assign Y = A * B;
endmodule

15
manual/PRESENTATION_ExAdv/sym_mul_map.v Normal file
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module \$mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
endmodule

5
manual/PRESENTATION_ExAdv/sym_mul_test.v Normal file
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module test(A, B, C, Y1, Y2);
input [7:0] A, B, C;
output [7:0] Y1 = A * B;
output [15:0] Y2 = A * C;
endmodule

6
manual/PRESENTATION_ExAdv/sym_mul_test.ys Normal file
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read_verilog sym_mul_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v;;
show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v